As a method of forming a transistor array with the highest density based on the minimum design rule F, a memory cell of DRAM (Dynamic Random Access Memory) is known (for example, see Non-Patent Document 1 (Y. K. Park, and 23 others, “Fully Integrated 56 nm DRAM Technology for 1 Gb DRAM”, “2007 Symposium on VLSI Technology Digest of Technical Papers”, pp. 190-191) and Non-Patent Document 2 (Changhyun Cho and 12 others, “A 6 F2 DRAM Technology in 60 nm era for Gigabit Densities”, “2005 Symposium on VLSI Technology Digest of Technical Papers”, pp. 36-37)). In the structure in related art, one transistor may be formed to have an area of 6F2 and the smallest cell area may be achieved as a planar transistor.